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ICS
2005
Tsinghua U.
13 years 10 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...
WWW
2002
ACM
14 years 5 months ago
Aliasing on the world wide web: prevalence and performance implications
Aliasing occurs in Web transactions when requests containing different URLs elicit replies containing identical data payloads. Conventional caches associate stored data with URLs ...
Terence Kelly, Jeffrey C. Mogul
TJS
2002
135views more  TJS 2002»
13 years 4 months ago
HPCVIEW: A Tool for Top-down Analysis of Node Performance
Although it is increasingly difficult for large scientific programs to attain a significant fraction of peak performance on systems based on microprocessors with substantial instr...
John M. Mellor-Crummey, Robert J. Fowler, Gabriel ...
COMPGEOM
2003
ACM
13 years 10 months ago
Cache-oblivious data structures for orthogonal range searching
We develop cache-oblivious data structures for orthogonal range searching, the problem of finding all T points in a set of N points in Êd lying in a query hyper-rectangle. Cache...
Pankaj K. Agarwal, Lars Arge, Andrew Danner, Bryan...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...