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ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
ISQED
2002
IEEE
137views Hardware» more  ISQED 2002»
9 years 7 months ago
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
9 years 11 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
DAC
2007
ACM
9 years 6 months ago
CAD Implications of New Interconnect Technologies
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
Louis Scheffer
ICCD
2005
IEEE
169views Hardware» more  ICCD 2005»
9 years 11 months ago
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...
Wei Zhang, Niraj K. Jha
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