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ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
13 years 10 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
VLSISP
2008
111views more  VLSISP 2008»
13 years 4 months ago
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
IWCMC
2010
ACM
13 years 2 months ago
Dynamic load balancing and throughput optimization in 3GPP LTE networks
Load imbalance that deteriorates the system performance is a severe problem existing in 3GPP LTE networks. To deal with this problem, we propose in this paper a load balancing fra...
Hao Wang, Lianghui Ding, Ping Wu, Zhiwen Pan, Nan ...
ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
14 years 1 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
13 years 11 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...