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DATE
2010
IEEE
184views Hardware» more  DATE 2010»
13 years 9 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
SIPS
2006
IEEE
13 years 10 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
DELTA
2010
IEEE
13 years 9 months ago
Notations for Multiphase Pipelines
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
Christopher T. Johnston, Donald G. Bailey, Paul J....
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 1 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
IPPS
1999
IEEE
13 years 8 months ago
Run-Time Selection of Block Size in Pipelined Parallel Programs
Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where crossprocessor data dependencie...
David K. Lowenthal, Michael James