36 search results - page 1 / 8 » Time Predictable CPU and DMA Shared Memory Access |
FPL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
HICSS
1995
IEEE
13 years 7 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
RTAS
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...