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MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
13 years 11 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
HPDC
2012
IEEE
11 years 7 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
CP
2008
Springer
13 years 7 months ago
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
Luca Benini, Michele Lombardi, Michela Milano, Mar...
GLOBE
2010
Springer
13 years 5 months ago
High Throughput Data-Compression for Cloud Storage
Abstract. As data volumes processed by large-scale distributed dataintensive applications grow at high-speed, an increasing I/O pressure is put on the underlying storage service, w...
Bogdan Nicolae
CLUSTER
2010
IEEE
12 years 9 months ago
Middleware support for many-task computing
Many-task computing aims to bridge the gap between two computing paradigms, high throughput computing and high performance computing. Many-task computing denotes highperformance co...
Ioan Raicu, Ian T. Foster, Mike Wilde, Zhao Zhang,...