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» Timing Analysis with Implicitly Specified False Paths
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VLSID
2000
IEEE
75views VLSI» more  VLSID 2000»
13 years 8 months ago
Timing Analysis with Implicitly Specified False Paths
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
Eugene Goldberg, Alexander Saldanha
DAC
2000
ACM
13 years 8 months ago
Removing user specified false paths from timing graphs
David Blaauw, Rajendran Panda, Abhijit Das
ASPDAC
2006
ACM
123views Hardware» more  ASPDAC 2006»
13 years 7 months ago
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
- We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent f...
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan...
DAC
2010
ACM
13 years 7 months ago
An efficient algorithm to verify generalized false paths
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
Olivier Coudert
ISSS
1998
IEEE
103views Hardware» more  ISSS 1998»
13 years 7 months ago
False Path Analysis Based on a Hierarchical Control Representation
False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time est...
Apostolos A. Kountouris, Christophe Wolinski