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» Timing Anomalies in Dynamically Scheduled Microprocessors
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RTSS
1999
IEEE
9 years 11 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
IPPS
1999
IEEE
9 years 11 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
9 years 12 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
10 years 16 days ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...
ISCAS
1999
IEEE
113views Hardware» more  ISCAS 1999»
9 years 11 months ago
Energy efficient software through dynamic voltage scheduling
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
Gangadhar Konduri, James Goodman, Anantha Chandrak...
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