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» Timing Driven Placement for Quasi Delay-Insensitive Circuits
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VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 4 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
13 years 10 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 7 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 7 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ISPD
1997
ACM
104views Hardware» more  ISPD 1997»
13 years 7 months ago
Timing driven placement in interaction with netlist transformations
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
Guenter Stenz, Bernhard M. Riess, Bernhard Rohflei...