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» Timing Yield Calculation Using an Impulse-Train Approach
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ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Fast Buffer Insertion for Yield Optimization Under Process Variations
With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique fo...
Ruiming Chen, Hai Zhou
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
13 years 11 months ago
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...
COLT
2006
Springer
13 years 9 months ago
Efficient Learning Algorithms Yield Circuit Lower Bounds
We describe a new approach for understanding the difficulty of designing efficient learning algorithms. We prove that the existence of an efficient learning algorithm for a circui...
Lance Fortnow, Adam R. Klivans
MSOM
2010
65views more  MSOM 2010»
12 years 12 months ago
The Optimal Composition of Influenza Vaccines Subject to Random Production Yields
The Vaccine and Related Biologic Products Advisory Committee meets at least once a year to decide the composition of the influenza vaccine in the U.S. Past evidence suggests that ...
Soo-Haeng Cho
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 2 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou