708 search results - page 2 / 142 » Timing closure: the solution and its problems |
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in in...
ENTCS
2008
13 years 5 months ago
2008
Timing Closure in presence of long global wire interconnects is one of the main current issues in System-onChip design. One proposed solution to the Timing Closure problem is Late...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
TVLSI
2002
13 years 5 months ago
2002
In this paper, we deal with arbitrarily shaped rectilinear module placement using the transitive closure graph (TCG) representation. The geometric meanings of modules are transpare...