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ISPD
1998
ACM
89views Hardware» more  ISPD 1998»
13 years 8 months ago
Timing metrics for physical design of deep submicron technologies
Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit d...
Lawrence T. Pileggi
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 1 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
13 years 8 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 8 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
13 years 10 months ago
Joint exploration of architectural and physical design spaces with thermal consideration
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen ...