Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit d...
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....