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ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
13 years 9 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
13 years 7 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
13 years 7 months ago
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
Abstract-- This paper presents a fundamental result on buffer sizing. Given an interconnection wire with n buffers evenly spaced along the wire, we would like to size all buffers s...
Sebastian Vogel, Martin D. F. Wong
DAC
2004
ACM
13 years 7 months ago
Practical repeater insertion for low power: what repeater library do we need?
In this paper, we investigate the problem of repeater insertion for low power under a given timing budget. We propose a novel repeater insertion algorithm to compute the optimal r...
Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 7 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah