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ICS
1995
Tsinghua U.
13 years 8 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
ISCAPDCS
2007
13 years 6 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
ISCAPDCS
2004
13 years 6 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
DPD
2008
136views more  DPD 2008»
13 years 5 months ago
A cache invalidation scheme for continuous partial match queries in mobile computing environments
The continuous partial match query is a partial match query whose result remains consistently in the client's memory. Conventional cache invalidation methods for mobile client...
Yon Dohn Chung
SIGARCH
2008
96views more  SIGARCH 2008»
13 years 5 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell