134 search results - page 27 / 27 » Tolerance Models in Hardware Description Languages |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...
SAMOS
2007
Springer
13 years 11 months ago
2007
Springer
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
ASWSD
2004
Springer
13 years 11 months ago
2004
Springer
The paper first presents the integration options of what we call the Timing Description Language (TDL) with MathWorks' Simulink tools. Based on the paradigm of logical executi...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
—Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it i...