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PARELEC
2006
IEEE
13 years 11 months ago
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments
Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decre...
Bernhard Fechner
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
13 years 11 months ago
Transient fault prediction based on anomalies in processor events
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
Satish Narayanasamy, Ayse Kivilcim Coskun, Brad Ca...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
13 years 10 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DAC
2003
ACM
14 years 6 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...