48 search results - page 1 / 10 » Tolerating data access latency with register preloading |
ICS
1992
Tsinghua U.
13 years 9 months ago
1992
Tsinghua U.
JUCS
2000
13 years 5 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
LCTRTS
2007
Springer
13 years 12 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
IPPS
2009
IEEE
14 years 12 days ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
DSN
2006
IEEE
13 years 11 months ago
2006
IEEE
Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to sof...