115 search results - page 1 / 23 » Topological Design of Interconnected LAN-MAN Networks |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
13 years 11 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
DATE
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
CDC
2010
IEEE
12 years 11 months ago
2010
IEEE
Abstract-- Communication networks provide a larger flexibility with respect to the control design of large-scale interconnected systems by allowing the information exchange between...
TCS
1998
13 years 4 months ago
1998
Recently a class of scalable multi-star optical networks is proposed in [2]. In this class of networks nodes are grouped into clusters. Each cluster employs a separate pair of bro...