10 search results - page 1 / 2 » Total power reduction in CMOS circuits via gate sizing and m... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...