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SIGMETRICS
2002
ACM
13 years 3 months ago
Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity
As processor microarchitectures continue to increase in complexity, so does the time required to explore the design space. Performing cycle
Jeanine Cook, Richard L. Oliver, Eric E. Johnson
HPCA
2012
IEEE
11 years 11 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
13 years 7 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
EUROPAR
2001
Springer
13 years 8 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
DAC
2009
ACM
14 years 4 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra