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» Towards Automated Power Gating of Registers using CoDeL
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ISCAS
2007
IEEE
78views Hardware» more  ISCAS 2007»
10 years 5 months ago
Towards Automated Power Gating of Registers using CoDeL
— In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we e...
Nainesh Agarwal, Nikitas J. Dimopoulos
SAMOS
2007
Springer
10 years 5 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
10 years 5 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
DAC
2000
ACM
11 years 16 days ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
DAC
2009
ACM
11 years 17 days ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
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