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» Towards hybrid last level caches for chip-multiprocessors
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ICPP
2009
IEEE
13 years 12 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
PDP
2010
IEEE
13 years 9 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...
IJHPCA
2010
117views more  IJHPCA 2010»
13 years 3 months ago
Fine-Grained Multithreading Support for Hybrid Threaded MPI Programming
As high-end computing systems continue to grow in scale, recent advances in multiand many-core architectures have pushed such growth toward more denser architectures, that is, mor...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
HOTOS
2009
IEEE
13 years 9 months ago
An End to the Middle
The last fifteen years has seen a vast proliferation of middleboxes to solve all manner of persistent limitations in the Internet protocol suite. Examples include firewalls, NATs,...
Colin Dixon, Arvind Krishnamurthy, Thomas E. Ander...