22 search results - page 1 / 5 » Trace Cache: A Low Latency Approach to High Bandwidth Instru... |
MICRO
1996
IEEE
13 years 8 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
TC
2002
13 years 4 months ago
2002
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...