17 search results - page 4 / 4 » Trace Reduction for Virtual Memory Simulations |
GLOBECOM
2009
IEEE
13 years 9 months ago
2009
IEEE
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...