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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 8 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
MICRO
1998
IEEE
111views Hardware» more  MICRO 1998»
13 years 9 months ago
Precise Register Allocation for Irregular Architectures
This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP registe...
Timothy Kong, Kent D. Wilken
IPL
2006
104views more  IPL 2006»
13 years 4 months ago
Optimal register allocation for SSA-form programs in polynomial time
This paper gives a constructive proof that the register allocation problem for a uniform register set is solvable in polynomial time for SSA-form programs. 2006 Elsevier B.V. All ...
Sebastian Hack, Gerhard Goos
CGO
2009
IEEE
13 years 11 months ago
Techniques for Region-Based Register Allocation
—Register allocation is an important component of every compiler and numerous studies have investigated ways to improve allocation quality or reduce allocation time. However, tec...
Ivan D. Baev
ICALP
2007
Springer
13 years 11 months ago
Aliased Register Allocation for Straight-Line Programs Is NP-Complete
Register allocation is NP-complete in general but can be solved in linear time for straight-line programs where each variable has at most one definition point if the bank of regis...
Jonathan K. Lee, Jens Palsberg, Fernando Magno Qui...