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» Trace-Driven Memory Simulation: A Survey
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DAGSTUHL
2000
13 years 5 months ago
Trace-Driven Memory Simulation: A Survey
Richard Uhlig, Trevor N. Mudge
AINA
2007
IEEE
13 years 10 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
SAMOS
2005
Springer
13 years 9 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 7 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ICS
2001
Tsinghua U.
13 years 8 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith