44 search results - page 1 / 9 » Trace-Level Speculative Multithreaded Architecture |
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectivel...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
IEEEPACT
2009
IEEE
13 years 11 months ago
2009
IEEE
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
TPDS
2010
13 years 3 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
EUROMICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...