141 search results - page 1 / 29 » Track Routing and Optimization for Yield |
TCAD
2008
13 years 4 months ago
2008
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
ISVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...