141 search results - page 2 / 29 » Track Routing and Optimization for Yield |
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...
SLIP
2005
ACM
13 years 10 months ago
2005
ACM
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
CDES
2006
13 years 6 months ago
2006
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...