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DATE
2003
IEEE
93views Hardware» more  DATE 2003»
13 years 10 months ago
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
Edwin Rijpkema, Kees G. W. Goossens, Andrei Radule...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
13 years 11 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
13 years 7 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch