5 search results - page 1 / 1 » Tradeoffs in Two-Level On-Chip Caching |
ISCA
1994
IEEE
13 years 8 months ago
1994
IEEE
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
ISCA
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...