59 search results - page 10 / 12 » Tradeoffs in transactional memory virtualization |
HPCA
2001
IEEE
14 years 6 months ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
OSDI
2002
ACM
14 years 6 months ago
2002
ACM
Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a...
NOCS
2007
IEEE
14 years 14 hour ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
INFOCOM
2009
IEEE
14 years 11 days ago
2009
IEEE
—Enterprise networks are increasingly adopting Layer 3 Multiprotocol Label Switching (MPLS) Virtual Private Network (VPN) technology to connect geographically disparate locations...
ICS
2004
Tsinghua U.
13 years 11 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...