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COMPSAC
2009
IEEE
10 years 4 months ago
Transaction Level Control for Application Execution on the SegBus Platform
Abstract—We define here a simple, low level control procedure definition, to support application implementation on a particular multiprocessor platform, namely the SegBus segme...
Tiberiu Seceleanu, Ivica Crnkovic, Cristina Cersch...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
10 years 6 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
JCS
1998
117views more  JCS 1998»
9 years 11 months ago
A Semantic-Based Transaction Processing Model for Multilevel Transactions
Multilevel transactions have been proposed for multilevel secure databases; in contrast to most proposals, such transactions allow users to read and write across multiple security...
Indrakshi Ray, Paul Ammann, Sushil Jajodia
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
10 years 4 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
LCTRTS
2010
Springer
10 years 6 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
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