15 search results - page 1 / 3 » Transaction Level Error Susceptibility Model for Bus Based S... |
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
DATE
2005
IEEE
13 years 6 months ago
2005
IEEE
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...