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IWSOC
2003
IEEE
96views Hardware» more  IWSOC 2003»
13 years 9 months ago
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic
Boris D. Andreev, Edward L. Titlebaum, Eby G. Frie...
VLSID
1996
IEEE
130views VLSI» more  VLSID 1996»
13 years 8 months ago
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents ...
S. Ramanathan, V. Visvanathan
INTEGRATION
2008
191views more  INTEGRATION 2008»
13 years 4 months ago
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Abstract: Hybrid-redundant number representation has provided a flexible framework for digitparallel addition in a manner that facilitates area-time tradeoffs for VLSI implementati...
Ghassem Jaberipur, Behrooz Parhami
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
14 years 4 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...