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» Transistor Flaring in Deep Submicron-Design Considerations
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VLSID
2002
IEEE
60views VLSI» more  VLSID 2002»
14 years 4 months ago
Transistor Flaring in Deep Submicron-Design Considerations
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R....
ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 8 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He