5 search results - page 1 / 1 » Transition Delay Fault Test Pattern Generation Considering S... |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
VTS
2007
IEEE
13 years 10 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...