17 search results - page 2 / 4 » Tuning Up the Performance of Constant-Time Distributed Sched... |
IEEEPACT
1998
IEEE
13 years 8 months ago
1998
IEEE
Compile-time scheduling is one approach to extract parallelism which has proved effective when the execution behavior is predictable. Unfortunately, the performance of most priori...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
SC
2003
ACM
13 years 9 months ago
2003
ACM
Computational grids hold great promise in utilizing geographically separated heterogeneous resources to solve large-scale complex scientific problems. However, a number of major ...
IPPS
1998
IEEE
13 years 8 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...