22 search results - page 2 / 5 » Two-level microprocessor-accelerator partitioning |
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
CCGRID
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— Recently we proposed algorithms for concurrent execution on multiple clusters [9]. In this case, data partitioning is done at two levels; first, the data is distribute...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
GD
2007
Springer
13 years 11 months ago
2007
Springer
We propose a layout algorithm for micro/macro graphs, i.e. relational structures with two levels of detail. While the micro-level graph is given, the macro-level graph is induced b...
IVC
2008
13 years 5 months ago
2008
We present a method for efficiently generating a representation of a multi-modal posterior probability distribution. The technique combines ideas from RANSAC and particle filterin...