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ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
14 years 7 days ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
CODES
2001
IEEE
13 years 9 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
RTSS
1998
IEEE
13 years 10 months ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...
HPCA
2005
IEEE
14 years 6 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
HPCA
1996
IEEE
13 years 10 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...