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HPCA
2005
IEEE
14 years 5 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
13 years 9 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ISPASS
2007
IEEE
13 years 11 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
SIGMETRICS
2010
ACM
145views Hardware» more  SIGMETRICS 2010»
12 years 11 months ago
Towards architecture independent metrics for multicore performance analysis
The prevalence of multicore architectures has made the performance analysis of multithreaded applications an intriguing area of inquiry. An understanding of locality effects and c...
Milind Kulkarni, Vijay S. Pai, Derek L. Schuff
MSE
2002
IEEE
135views Hardware» more  MSE 2002»
13 years 9 months ago
The Impact of SMT/SMP Designs on Multimedia Software Engineering - A Workload Analysis Study
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
Yen-Kuang Chen, Rainer Lienhart, Eric Debes, Matth...