2 search results - page 1 / 1 » Unified Challenges in Nano-CMOS High-Level Synthesis |
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...