3 search results - page 1 / 1 » Using Cluster-Based Logic Blocks and Timing-Driven Packing t... |
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
FPGA
1997
ACM
13 years 9 months ago
1997
ACM
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...