39 search results - page 2 / 8 » Using Integer Equations for High Level Formal Verification P... |
CAV
2009
Springer
14 years 5 months ago
2009
Springer
We provide a verification technique for a class of programs working on integer arrays of finite, but not a priori bounded length. We use the logic of integer arrays SIL [13] to spe...
FMAM
2010
13 years 3 months ago
2010
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...