Sciweavers

111 search results - page 2 / 23
» Using Multiple Memory Access Instructions for Reducing Code ...
Sort
View
TVLSI
2002
98views more  TVLSI 2002»
13 years 4 months ago
Minimizing memory access energy in embedded systems by selective instruction compression
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
HPCC
2009
Springer
13 years 9 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
13 years 10 months ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
CODES
2005
IEEE
13 years 6 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
LCTRTS
2010
Springer
13 years 11 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...