17 search results - page 4 / 4 » Using Process-Level Redundancy to Exploit Multiple Cores for... |
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...