259 search results - page 2 / 52 » Using Transformations and Verification in Circuit Design |
CJ
2010
13 years 5 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
ASYNC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
HICSS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a graph transformation based approach to design pattern evolution. An evolution of a design pattern includes modifications of pattern elements, such as classes...