54 search results - page 10 / 11 » Using a Swap Instruction to Coalesce Loads and Stores |
CAV
1999
Springer
13 years 10 months ago
1999
Springer
Abstract. In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition ca...
ICS
2001
Tsinghua U.
13 years 10 months ago
2001
Tsinghua U.
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
HOTOS
2003
IEEE
13 years 11 months ago
2003
IEEE
Cerium is a trusted computing architecture that protects a program’s execution from being tampered while the program is running. Cerium uses a physically tamperresistant CPU and...
HPCA
2000
IEEE
13 years 10 months ago
2000
IEEE
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
LCTRTS
2007
Springer
13 years 12 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...