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» Using hardware transactional memory for data race detection
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IPPS
2009
IEEE
13 years 11 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
HPCA
2008
IEEE
14 years 4 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
13 years 11 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
ACMMSP
2006
ACM
257views Hardware» more  ACMMSP 2006»
13 years 10 months ago
Memory models for open-nested transactions
Open nesting provides a loophole in the strict model of atomic transactions. Moss and Hosking suggested adapting open nesting for transactional memory, and Moss and a group at Sta...
Kunal Agrawal, Charles E. Leiserson, Jim Sukha
ASPLOS
2006
ACM
13 years 10 months ago
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkate...