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ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
13 years 11 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ICS
1999
Tsinghua U.
13 years 9 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
ISCAPDCS
2007
13 years 6 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
ICASSP
2011
IEEE
12 years 9 months ago
Increasing discriminative capability on MAP-based mapping function estimation for acoustic model adaptation
In this study, we propose increasing discriminative power on the maximum a posteriori (MAP)-based mapping function estimation for acoustic model adaptation. Based on the effective...
Yu Tsao, Ryosuke Isotani, Hisashi Kawai, Satoshi N...
IEEEPACT
2002
IEEE
13 years 10 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...